One or more aspects of the present invention relate in general to the field of hardware and system software of computer systems, and in particular to a method for address translation and a corresponding address translation unit. Still more particularly, one or more aspects of the present invention relate to a data processing program and a computer program product for address translation.
In today's computer systems like a zGryphon processor core an address translation unit is assigned for translating virtual addresses (VA) to absolute addresses (AA) by means of multiple levels of translation tables as defined in the z/Architecture, for example. The address translation unit receives address translation requests from a Load Store Unit (LSU), a Coprocessor (CoP) for data compression and cryptography, and/or an Instruction Fetch Unit (IFU), for example, wherein the LSU has the highest priority and the IFU has the lowest priority.
In the address translation unit a translation request with the highest priority is gated through an input multiplexer into a current request register. Every translation request comes along with a virtual address (VA), an Address Space Control Element (ASCE) and some additional qualifiers. The ASCE designates the starting address of the highest level translation table involved in this request. As soon as the current request register has been loaded, a lookup operation of a translation look aside buffer as fast address translation is performed, and in case of a hit, the respective absolute address (AA) is gated through a result multiplexer and returned to a corresponding requestor as translation result.
If the translation look aside buffer lookup does not hit, the respective VA is to be translated by a translation engine using means of translation tables residing in an absolute storage region. The translation engine therefore has an interface for translation table fetches. Several table fetches may be required to complete a single translation request and the result is finally returned to the requestor via the result multiplexer and is also stored into the translation look aside buffer, to become available for a lookup hit by subsequent translation requests.
In case a translation request does not hit in the translation look aside buffer, the translation table fetches to be performed by the translation engine may consume about 10 to 1000 cycles, dependent in which level of the cache hierarchy the required entry currently resides. During these table fetches, the translation engine is completely idle; while another translation request may still be waiting for accept.
In the U.S. Pat. No. 6,418,522 B1 “TRANSLATION LOOK ASIDE BUFFER FOR VIRTUAL MEMORY SYSTEMS” by Gaertner et al., which is hereby incorporated herein by reference it its entirety, a translation look aside buffer arrangement is disclosed.
The disclosed translation look aside buffer arrangement uses two buffers, a small first level translation look aside buffer and a larger second level translation look aside buffer. The second level translation look aside buffer feeds address information to the first level translation look aside buffer when the desired virtual address is not contained in the first level translation look aside buffer. Further the second level translation look aside buffer is structured to comprise two n-way set associative sub-units of which one, a higher level unit, covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. Additionally some address information holds some number of middle level virtual address bits, i.e. 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit. Thus, the same information is used as tag information in the lower level sub-unit and is used herein as a quick reference in any lookup operation in order to find the absolute address of the concerned virtual address. Further, the commonly used status bits, like, e.g., valid bits, are used in both translation look aside buffer structures, too.
In the Patent Application Publication US 2009/0187731 A1 “METHOD FOR ADDRESS TRANSLATION IN VIRTUAL MACHINES” by Deutschle et al., which is hereby incorporated herein by reference in its entirety, a method for address translation in a system running multiple levels of virtual machines is disclosed.
The virtual machines are containing a hierarchically organized translation look aside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a translation look aside buffer for some higher level address translation levels, and the second sub-unit comprising a translation look aside buffer for some lower level address translation levels, and the second sub-unit being arranged to store translation look aside buffer index address information of the upper level sub-unit as tag information in its lower level translation look aside buffer structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels, and buffering the intermediate translation results in the translation look aside buffer.